The present invention relates generally to novel integrated circuit packages that include a new family of miniature antennas in the package. The present invention allows the integration of a full wireless system into a single component.
There is a trend in the semiconductor industry towards the so-called System on Chip (SoC) and System on Package (SoP) concepts. This means integrating as many components of an electronic system as possible (processors, memories, logic gates, biasing circuitry, etc.) into a single semiconductor chip (or “die”) (SoC) or at least into a single integrated circuit package (SoP). The full integration of systems or subsystems into a single chip or package provides many advantages in terms of cost, size, weight, consumption, performance and product design complexity. Several electronics components for consumer applications, such as handsets, wireless devices, personal digital assistants (PDA) or personal computers are becoming more and more integrated into SoP/SoC products.
The concept of integrating a full wireless system into a SoC/SoP device (FWSoC and FWSoP) is especially attractive owing to the tremendous growth and success of cellular and wireless systems. In particular, there is a new generation of short/medium range wireless applications such as Bluetooth™, Hyperlan, IEEE802.11 and ultra wide band (UWB) systems where the progressive system integration into a single, compact product is becoming a key success factor (see for instance S. Harris and H. Johnston, “Handset industry debate Bluetooth chip options”, WirlessEurope, May 2002). Recently, several vendors (for example www.infineon.com, www.st.com, www.epson.com www.csr.com) are offering SoC or SoP products for applications that integrate everything into the chip or package, except for the antenna. The reason the antenna is excluded is that its integration into the SoC or SoP is a major engineering challenge in the product development, mainly due to the reduced size of the commercial SoP and SoC packages and the well-known constraints on the performance of miniature antennas.
There have been reported several attempts to integrate an antenna inside a semiconductor die or chip, which die or chip also includes an electronic system or radio frequency (RF) front-end (see for example D. Singh, C. Kaliakis, P. Gardner, P. S. Hall, Small H-Shaped Antennas for MMIC Applications, IEEE Trans. on Antennas and Propagation, vol. 48, no. 7, July 2000; D. W. Griffin, A. J. Partfitt, Electromagnetic Design Aspects of Packages for Monolithic Microwave Integrated Circuit-Based Arrays with Integrated Antenna Elements, IEEE Trans. on Antennas and Propagation, vol. 43, no. 9 September 1995; P. S. Hall, System Applications: The Challenge for Active Integrated Antennas, APS2000 Millennium Conference, April 2002; I. Papapolymerou, R. F. Drayton, L. P. B. Katehi, Micromachined Patch Antennas, IEEE Trans. on Antennas and Propagation, vol. 46, no. 2 February 1998; J. Zhao, S. Raman, Design of Chip-Scale Patch Antennas for 5-6 GHz Wireless Microsystem, Antennas and Propagation Society, 2001 IEEE International Symp., Volume: 2, 2001; and U.S. Pat. No. 6,373,447). These designs feature two important limitations: first the operating frequency must be large enough to allow a conventional antenna to fit inside the chip; second the antenna performance is poor in terms of gain, mainly due to the losses in the semiconductor material. According to D. Singh, et al., the smallest frequency in which an antenna has been integrated together with an electronic system inside the same was 5.98 GHz. Typical gains that have been achieved with such designs are around −10 dBi.
In general, there is a trade-off between antenna performance and miniaturization. The fundamental limits on small antennas were theoretically established by H. Wheeler and L. J. Chu in the middle 1940's. They stated that a small antenna has a high quality factor (Q) because of the large reactive energy stored in the antenna vicinity compared to the radiated power. Such a high quality factor yields a narrow bandwidth; in fact, the fundamental derived in such theory imposes a maximum bandwidth given a specific size of a small antenna. Related to this phenomenon, it is also known that a small antenna features a large input reactance (either capacitive or inductive) that usually has to be compensated with an external matching/loading circuit or structure. It also means that it is difficult to pack a resonant antenna into a space which is small in terms of the wavelength at resonance. Other characteristics of a small antenna are its small radiating resistance and its low efficiency (see R. C. Hansen, Fundamental Limitations on Antennas, Proc. IEEE, vol. 69, no. 2, February 1981).
Some antenna miniaturization techniques rely basically on the antenna geometry to achieve a substantial resonant frequency reduction while keeping efficient radiation. For instance patent WO01/54225 discloses a set of space-filling antenna geometries (SFC) that are suitable for this purpose. Another advantage of such SFC geometries is that in some cases they feature a multiband response.
The dimension (D) is a commonly used parameter to mathematically describe the complexity of some convoluted curves. There exist many different mathematical definitions of dimension but in the present document the box-counting dimension (which is well-known to those skilled in advanced mathematics theory) is used to characterize some embodiments (see discussion on the mathematical concept of dimension in for instance W. E. Caswell and J. A. Yorke, Invisible errors in dimension calculations: geometric and systematic effects, Dimensions and Entropies in Chaotic Systems, G.Mayer-Kress edit., Springer-Verlag, Berlin 1989, second edition pp. 123-136, and K. Judd, A. I. Mees, Estimating dimensions with confidence, International Journal of Bifurcation and Chaos 1,2 (1991) 467-470).
It should be apparent that the present invention is substantially different from some prior-art designs called chip-antennas (see for instance H. Tanidokoro, N. Konishi, E. Hirose, Y. Shinohara, H. Arai, N. Goto, I-Wavelength Loop Type Dielectric Chip Antennas, Antennas and Propagation Society International Symposium, 1998, IEEE, vol. 4, 1998; Electromagnetically coupled dielectric chip antenna, Matsushima, H.; Hirose, E.; Shinohara, Y.; Arai, H.; Golo, N. Antennas and Propagation Society International Symposium, IEEE, Vol. 4, 1998). Those are typically single component antenna products that integrate only the antenna inside a surface-mount device. To achieve the necessary wavelength compression, those antennas are mainly constructed using high permittivity materials such as ceramics. The drawbacks of using such high permittivity materials are that the antenna has a very narrow bandwidth, the material introduces significant losses, and the manufacturing procedure and materials are not compatible with most current chip or package manufacturing techniques; therefore they do not currently include other components or electronics besides the antenna, and they are not suitable for a FWSoC or FWSoP. On the contrary, the present invention relies on the specific novel design of the antenna geometry and its ability to use the materials that are currently being used for integrated circuit package construction, so that the cost is minimized while allowing a smooth integration with the rest of the system.
There have been recently disclosed some RF SoP configurations that also include also antennas on the package. Again, most of these designs rely on a conventional microstrip, shorted patch or PIFA antenna that is suitable for large frequencies (and therefore small wavelengths) and feature a reduced gain. In the paper K. Lim, S. Pinel, M. Davis, A. Sutono, C. Lee, D. Heo, A. Obatoynbo, J. Laskar, E. Tantzeris. R. Tummala, RF-System-On-Package (SOP) for Wireless Communications, IEEE Microwave Magazine, vol. 3, no. 1, March 2002, a SoP including an RF front-end with an integrated antenna is described. The antenna comprises a microstrip patch backed by a cavity which is made with shorting pins and operates at 5.8 GHz. As mentioned in the paper, it is difficult to extend those designs in the 1-6 GHz frequency range where most current wireless and cellular services are located, mainly due to the size of conventional antennas at such large wavelengths. Another design for an antenna on a package is disclosed in Y. P. Zhang, W. B. Li, Integration of a Planar Inverted F Antenna on a Cavity-Down Ceramic Ball Grid Array Package, IEEE Symp. on Antennas and Propagation, June 2002. Although the antenna operates at the Bluetooth™ band (2.4 GHz), the IC package is substantially large (15×15 mm) and the antenna performance is poor (gain is below −9 dBi).
Patent application EP1126522 describes a particular double S-shaped antenna design that is mounted on a BGA package. Although no precise data is given on the package size in the application, typically, S-shaped slot antennas resonate at a wavelength on the order of twice the unfolded length of the S-shaped pattern. Again, this makes the whole package too large for typical wireless applications where the wavelength is above 120 mm. Also, this design requires a combination with high permittivity materials that, in turn, reduce the antenna bandwidth, increase its cost and decreases the overall antenna efficiency.
Regarding the package construction and architecture, there are several standard configurations depending mainly on the application. Some basic architectures are: single-in-line (SIL), dual-in-line (DIL), dual-in-line with surface mount technology DIL-SMT, quad-flat-package (QFP), pin grid array (PGA) and ball grid array (BGA) and small outline packages. Other derivatives are for instance: plastic ball grid array (PBGA), ceramic ball grid array (CBGA), tape ball grid array (TBGA), super ball grid array (SBGA), micro ball grid array □BGA®. Some of these configurations are present in their CSP (Chip Scale Package) versions, wherein the semiconductor chip or die typically fills up to an 85% of the package area. The interconnection of those packages with the semiconductor chip or die can be done with several standard processes and technologies as well, mainly wire-bonding, tape automated bonding and flip-chip. A description of several standard packaging architectures can be found in the websites of several package manufacturers, such as for instance www.amkor.com (see also L. Halbo, P. Ohlckers, Electronic Components, Packaging and Production, ISBN.82-992193-2-9).
In the last few years, several improvements in packaging technology have appeared mainly due to the development of Multichip Module (MCM) applications (see for instance N. Sherwani, Q. Yu, S. Badida, Introduction to Multi Chip Modules, John Wiley & Sons, 1995). Those consist of an integrated circuit package that typically contains several chips (i.e., several semiconductor dies) and discrete miniature components (biasing capacitors, resistors, inductors). Depending on the materials and manufacturing technologies, MCM packages are classified in three main categories: laminated (MCM-L), ceramic (MCM-C) and deposited (MCM-D). Some combinations of them are also possible, such as MCM-L/D and other derivations such as Matsushita ALIVH. These MCM packaging techniques cover a wide range of materials for the substrate (for instance E-glass/epoxy, E-glass/polyimide, woven Kevlar/epoxy, s-glass/cyanate ester, quartz/polymide, thermount/HiTa epoxy, thermount/polyimide, thermount/cyanate ester, PTFE, RT-Duroid 5880, Rogers RO3000® and RO4000®, polyiolefin, alumina, sapphire, quartz glass, Corning glass, beryllium oxide and even intrinsic GaAs and silicon) and manufacturing processes (thick film, thin film, silicon thin film, polymer thin film, LTCC, HTCC).